1. Field of the Invention
The present invention relates to integrated circuit technology including new memory cell structures for flash memory.
2. Description of Related Art
In popular architectures for flash memory, the memory cells are either constructed in series between a bitline and a reference line (e.g. NAND Flash), or connected in parallel between bitlines and reference lines (e.g. NOR or AND Flash). For NAND Flash, 16 or 32 transistors are connected in series, and the reading current passes through all the series connected cells. This greatly reduces the reading current. Typically the read current is smaller than 1 μA, and the read random access time for a single bit can be about 20 μsec.
For NOR and AND Flash, the memory transistors are connected in parallel, so that larger reading current can be provided (typically larger than 20 μA). The larger reading current enables fast random access read applications (typically 70-100 nanoseconds for single bit reading). However, relatively high voltages are used. Thus, as the device sizes become smaller, so-called short channel effects like punch-through become difficult to control.
One technology for controlling the short channel effect is based on “pocket implants” (also called “channel stop implants”), formed by implanting pockets in the channel near the source and drain junctions with higher concentrations of dopants having the same conductivity type as the channel. See, e.g., Matsumoto et al., U.S. Pat. No. 6,933,565, issued 23 Aug. 2005. As the channel lengths of the memory cells shrink the space in the channel available for pocket implants shrinks as well, and pocket implant technology becomes difficult to control precisely.
Another technique which has been explored to control short channel effects is based on the use of dielectric plugs between the source/drain junctions of transistors and the channel of the transistor. See, e.g.; Teng et al., U.S. Pat. No. 4,963,502, issued 16 Oct. 1990; Wang et al., U.S. Pat. No. 6,812,103, issued 2 Nov. 2004; and Park, U.S. Pat. No. 6,858,505, issued 22 Feb. 2005. The dielectric plugs block the electric fields tending to induce short channel effects, effectively enabling devices with smaller channel lengths. However, the dielectric plug techniques involve complex processing techniques, limiting their applicability, and are not believed to have been successfully applied to memory technologies.
Another problem with shrinking memory cells, particularly for NOR Flash architectures, concerns the need for low resistance source and drain terminals, particularly in arrays using doped source/drain lines in the semiconductor substrate (sometimes called “buried diffusion lines”) for local bitlines and source lines. As these doped semiconductor lines become narrower and shallower, their resistivity increases. High resistance in the current path for reading the cells can slow down the read cycle, require higher voltage operation, produce waste heat and otherwise affect performance of the device.
It is desirable therefore to provide memory array structures and methods for manufacturing such structures for high speed flash memory devices that are both scalable to small channel lengths, and address issues related to the short channel effect.